// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_ap_mg_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:15 Create file
// ******************************************************************************

#ifndef __HIPCIEC_AP_MG_REG_REG_OFFSET_H__
#define __HIPCIEC_AP_MG_REG_REG_OFFSET_H__

/* HIPCIEC_AP_MG_REG Base address of Module's Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE                       (0x8000)

/******************************************************************************/
/*                      HiPCIECTRL40V200 HIPCIEC_AP_MG_REG Registers' Definitions                            */
/******************************************************************************/

#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_ERR_MAPPING_REG            (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x0)    /* CE(ERR_COR)/UNF(ERR_NONFATAL)/UF(ERR_FATAL) mapping to ERI/FHI */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_ENA_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x8)    /* CE(ERR_COR) interrupt enable of Root Port */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_UNF_ENA_REG                (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10)   /* UNF(ERR_NONFATAL) interrupt enable of Root Port */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_UF_ENA_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x18)   /* UF(ERR_FATAL) interrupt enable of Root Port */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_STATUS_REG              (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x20)   /* CE(ERR_COR) interrupt status of Root Port */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_UNF_STATUS_REG             (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x28)   /* UNF(ERR_NONFATAL)  interrupt status of Root Port */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_UF_STATUS_REG              (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x30)   /* UF(ERR_FATAL)  interrupt status of Root Port */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x40)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x48)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x50)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x58)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x60)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x68)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_6_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x70)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_7_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x78)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_8_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x80)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_9_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x88)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_10_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x90)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_11_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x98)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_12_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0xA0)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_13_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0xA8)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_14_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0xB0)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_15_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0xB8)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_16_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0xC0)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_17_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0xC8)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_18_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0xD0)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_19_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0xD8)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_20_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0xE0)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_21_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0xE8)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_22_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0xF0)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_23_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0xF8)   /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_24_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x100)  /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_25_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x108)  /* 16-bit CE(ERR_COR) counter register for the Port port_idx */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_PCIE_LOCAL_ERR_TYPE_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x200)  /* PCIe loacl err type */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_CFG_INTX_CLR_EN_REG             (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x400)  /* Config the INTx clear of each Port. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_CFG_INTX_DEASSERT_MODE_REG      (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x404)  /* Config the INTx deassert mode of each Port. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_CFG_ODR_DISP_CTRL_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x408)  /* IOB RX dispatch dfx select control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_DFX_PORT_INTX_PENDING_CNT_REG   (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x500)  /* INTx Pending Conute DFX register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_DFX_CORE_INTX_CNT_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x504)  /* INTx Conute DFX register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_DFX_PORT_ERR_COR_CNT_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x510)  /* Correctable Error Msg Conute DFX register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_DFX_CORE_ERR_MSG_CNT_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x514)  /* Error Msg DFX register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_DFX_ODR_P_CNT_REG               (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x520)  /* Odr channel post tlp counter register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_DFX_ODR_NP_CNT_REG              (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x524)  /* Odr channel non post tlp counter register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_AP_RAM_TIMING_CFG0_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x800)  /* sram timing config for all of the SRAM in AP module */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_AP_RAM_TIMING_CFG1_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x804)  /* sram timing config for all of the SRAM in AP module.The tp_ram_tmod is different with AP_RAM_TIMING_CFG0.Not used so far. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TOP_CTRL_REG               (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1000) /* MCTP Top Control Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_CTRL_0_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1004) /* MCTP Control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_CTRL_1_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1204) /* MCTP Control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_CTRL_2_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1404) /* MCTP Control Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RSV0_0_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1008) /* MCTP Reserved Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RSV0_1_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1208) /* MCTP Reserved Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RSV0_2_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1408) /* MCTP Reserved Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RSV1_0_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x100C) /* MCTP Reserved Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RSV1_1_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x120C) /* MCTP Reserved Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RSV1_2_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x140C) /* MCTP Reserved Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RSV2_0_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1010) /* MCTP Reserved Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RSV2_1_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1210) /* MCTP Reserved Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RSV2_2_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1410) /* MCTP Reserved Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_INT_MAPPING_0_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1014) /* Interrupt mapping 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_INT_MAPPING_1_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1214) /* Interrupt mapping 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_INT_MAPPING_2_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1414) /* Interrupt mapping 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_INTRPT_MASK_0_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1020) /* Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_INTRPT_MASK_1_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1220) /* Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_INTRPT_MASK_2_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1420) /* Interrupt Mask Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_INTRPT_STAT_0_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1024) /* Interrupt Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_INTRPT_STAT_1_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1224) /* Interrupt Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_INTRPT_STAT_2_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1424) /* Interrupt Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_0_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1028) /* RX interrupt control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_1_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1228) /* RX interrupt control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_2_REG          (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1428) /* RX interrupt control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_0_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1030) /* RX Queue Pempty Threshold Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_1_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1230) /* RX Queue Pempty Threshold Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_2_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1430) /* RX Queue Pempty Threshold Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_0_REG    (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1040) /* RX Queue base address register. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_1_REG    (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1240) /* RX Queue base address register. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_2_REG    (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1440) /* RX Queue base address register. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1044) /* RX Queue base address register. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1244) /* RX Queue base address register. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1444) /* RX Queue base address register. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1048) /* RX Queue Depth. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1248) /* RX Queue Depth. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1448) /* RX Queue Depth. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1050) /* RX Queue Head Pointer. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1250) /* RX Queue Head Pointer. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1450) /* RX Queue Head Pointer. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1054) /* RX Queue Tail Pointer. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1254) /* RX Queue Tail Pointer. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1454) /* RX Queue Tail Pointer. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_0_REG    (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1060) /* TX Queue base address register. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_1_REG    (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1260) /* TX Queue base address register. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_2_REG    (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1460) /* TX Queue base address register. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1064) /* TX Queue base address register. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1264) /* TX Queue base address register. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1464) /* TX Queue base address register. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1068) /* TX Queue Depth. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1268) /* TX Queue Depth. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1468) /* TX Queue Depth. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1070) /* TX Queue Head Pointer. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1270) /* TX Queue Head Pointer. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1470) /* TX Queue Head Pointer. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1074) /* TX Queue Tail Pointer. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1274) /* TX Queue Tail Pointer. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1474) /* TX Queue Tail Pointer. */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1080) /* RX AXI Write Error Address */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1280) /* RX AXI Write Error Address */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_2_REG (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1480) /* RX AXI Write Error Address */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_0_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1084) /* RX AXI Write Error Address */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_1_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1284) /* RX AXI Write Error Address */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_2_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1484) /* RX AXI Write Error Address */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK0_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10A0) /* TLP Header Check Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK0_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12A0) /* TLP Header Check Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK0_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14A0) /* TLP Header Check Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK1_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10A4) /* TLP Header Check Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK1_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12A4) /* TLP Header Check Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK1_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14A4) /* TLP Header Check Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK2_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10A8) /* TLP Header Check Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK2_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12A8) /* TLP Header Check Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK2_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14A8) /* TLP Header Check Register 2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_0_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10B0) /* Counter for error tx message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_0_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12B0) /* Counter for error tx message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_0_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14B0) /* Counter for error tx message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_1_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10B4) /* Counter for error tx message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_1_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12B4) /* Counter for error tx message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_1_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14B4) /* Counter for error tx message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_0_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10B8) /* Counter for error rx message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_0_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12B8) /* Counter for error rx message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_0_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14B8) /* Counter for error rx message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_1_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10BC) /* Counter for error rx message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_1_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12BC) /* Counter for error rx message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_1_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14BC) /* Counter for error rx message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_DATA_FIFO_STATUS_0_REG     (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10C0) /* FIFO status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_DATA_FIFO_STATUS_1_REG     (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12C0) /* FIFO status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_DATA_FIFO_STATUS_2_REG     (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14C0) /* FIFO status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10C4) /* Threshold to drop RX message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12C4) /* Threshold to drop RX message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14C4) /* Threshold to drop RX message */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_CNT_0_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10C8) /* RX dropped message counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_CNT_0_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12C8) /* RX dropped message counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_CNT_0_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14C8) /* RX dropped message counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_0_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10CC) /* MCTP TX Routing Error Counter 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_0_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12CC) /* MCTP TX Routing Error Counter 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_0_2_REG (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14CC) /* MCTP TX Routing Error Counter 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_1_0_REG (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10D0) /* MCTP TX Routing Error Counter 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_1_1_REG (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12D0) /* MCTP TX Routing Error Counter 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_1_2_REG (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14D0) /* MCTP TX Routing Error Counter 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_0_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10D4) /* MCTP TX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_0_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12D4) /* MCTP TX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_0_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14D4) /* MCTP TX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_1_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10D8) /* MCTP TX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_1_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12D8) /* MCTP TX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_1_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14D8) /* MCTP TX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_2_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10DC) /* MCTP TX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_2_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12DC) /* MCTP TX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_2_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14DC) /* MCTP TX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_0_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10E0) /* MCTP RX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_0_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12E0) /* MCTP RX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_0_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14E0) /* MCTP RX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_1_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10E4) /* MCTP RX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_1_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12E4) /* MCTP RX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_1_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14E4) /* MCTP RX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_2_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10E8) /* MCTP RX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_2_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12E8) /* MCTP RX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_2_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14E8) /* MCTP RX Packet Statistic */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_DEBUG_FSM_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10EC) /* FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_DEBUG_FSM_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12EC) /* FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_DEBUG_FSM_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14EC) /* FSM Status Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_HDR_MATCH_STAT_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10F0) /* MCTP Header Match Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_HDR_MATCH_STAT_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12F0) /* MCTP Header Match Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_HDR_MATCH_STAT_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14F0) /* MCTP Header Match Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_DFX_0_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10F4) /* MCTP DFX Control Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_DFX_1_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12F4) /* MCTP DFX Control Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_DFX_2_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14F4) /* MCTP DFX Control Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_ECC_ERR_INJECTION_0_REG    (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10F8) /* MCTP ECC Error Injection */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_ECC_ERR_INJECTION_1_REG    (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12F8) /* MCTP ECC Error Injection */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_ECC_ERR_INJECTION_2_REG    (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14F8) /* MCTP ECC Error Injection */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_0_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x10FC) /* MCTP RX 1-bit ECC Error Counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_1_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x12FC) /* MCTP RX 1-bit ECC Error Counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_2_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x14FC) /* MCTP RX 1-bit ECC Error Counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_0_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1110) /* MCTP RX 2-bit ECC Error Counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_1_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1310) /* MCTP RX 2-bit ECC Error Counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_2_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1510) /* MCTP RX 2-bit ECC Error Counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_0_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1114) /* MCTP TX 1-bit ECC Error Counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_1_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1314) /* MCTP TX 1-bit ECC Error Counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_2_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1514) /* MCTP TX 1-bit ECC Error Counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_0_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1118) /* MCTP TX 2-bit ECC Error Counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_1_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1318) /* MCTP TX 2-bit ECC Error Counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_2_REG  (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1518) /* MCTP TX 2-bit ECC Error Counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_0_REG      (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x111C) /* MCTP Dropped Header DW0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_1_REG      (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x131C) /* MCTP Dropped Header DW0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_2_REG      (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x151C) /* MCTP Dropped Header DW0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_0_REG      (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1120) /* MCTP Dropped Header DW1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_1_REG      (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1320) /* MCTP Dropped Header DW1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_2_REG      (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1520) /* MCTP Dropped Header DW1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_0_REG      (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1124) /* MCTP Dropped Header DW2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_1_REG      (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1324) /* MCTP Dropped Header DW2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_2_REG      (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1524) /* MCTP Dropped Header DW2 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_0_REG      (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1128) /* MCTP Dropped Header DW3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_1_REG      (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1328) /* MCTP Dropped Header DW3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_2_REG      (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1528) /* MCTP Dropped Header DW3 */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_AXUSER_0_REG               (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x112C) /* MCTP AXUSER */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_AXUSER_1_REG               (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x132C) /* MCTP AXUSER */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_AXUSER_2_REG               (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x152C) /* MCTP AXUSER */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1130) /* MCTP RX memory write request Stream ID */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1330) /* MCTP RX memory write request Stream ID */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1530) /* MCTP RX memory write request Stream ID */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1134) /* MCTP TX memory read request Stream ID */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1334) /* MCTP TX memory read request Stream ID */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x1534) /* MCTP TX memory read request Stream ID */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_TX_BROADCAST_DFX_REG       (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x2018) /* MCTP_RC Broadcast */
#define HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_MCTP_RX_DISPATCH_DFX_REG        (HiPCIECTRL40V200_HIPCIEC_AP_MG_REG_BASE + 0x201C) /* MCTP RX Dispatch */

#endif // __HIPCIEC_AP_MG_REG_REG_OFFSET_H__
